Across all sectors, industries, and geographies, demands continue for the electronic industry to provide products that are lighter, faster, smaller, multi-functional, more reliable, and more cost-effective. In order to meet these expanding requirements of so many and varied consumers, more electrical circuits need to be more highly integrated to provide the functions demanded. Across virtually all applications, there continues to be growing demand for reducing size, increasing performance, and improving features of integrated circuits.
The seemingly endless restrictions and requirements are no more visible than with products in our daily lives. Smaller and denser integrated circuits are required in many portable electronic products, such as cell phones, portable computers, voice recorders, etc. as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc.
As the demand grows for smaller electronic products with more features, manufacturers are seeking ways to include more features as well as reduce the size of the integrated circuits. However, increasing the density of integration in integrated circuits may be expensive and have technical limitations. Though technology continues its growth to once unimagined extents, practical limits of individual integrated circuits do exist.
To meet these needs, three-dimensional type integrated circuit packaging techniques have been developed and used. Packaging technologies are increasingly using smaller form factors with more circuits in three-dimensional packages. In general, package stacks made by stacking packages and stacked chip packages made by stacking chips in a package have been used.
A Package-on-Package (PoP), as its name implies, is a semiconductor packaging innovation that involves the stacking of two or more packages on top of one another. The PoP is a three dimensional (3D) package in which a fully tested package, such as single die Ball-Grid-Array or stacked die Ball-Grid-Array (typically memory die) is stacked on a bottom PoP package which usually contains a logic device or logic device combination (logic plus logic, logic plus analog, etc.).
The Fan-in Package-on-Package (Fi-PoP) package system is a stacked package system that allows stacking multiple logic, analog, and memory packages in the bottom PoP package. The Fi-PoP package system structure allows for smaller conventional memory packages to be mounted with center ball grid array patterns on the top PoP package.
The Fi-PoP package system also accommodates larger die sizes in a reduced footprint as compared to conventional PoP designs. The footprint reflects what is typically the maximum dimension of the package, namely, the x-y dimension of the package in the horizontal plane.
The bottom Fi-PoP (Fi-PoPb) provides the flexibility to package a single device or multiple devices (logic, analog or memory), while providing land pads on the top center of the package to allow for another package or components to be reflowed on top. The Fi-PoPb can also incorporate a fully tested Internal Stacking Module (ISM) package.
In addition, the Fi-PoPb can be smaller than current standard bottom PoP as interconnection is done by means of wire bonds, not solder balls at the edge of the bottom PoP. The package mounted on top of the Fi-PoPb can be a center Ball-Grid-Array package, such as a typical stacked die memory package or multiple packages or components. The top package can be significantly smaller than the current standard top PoP since it is no longer coupled to bottom package by peripheral solder ball connections. The result is a flexible 3D stacked package solution with smaller footprint, less board mount issues (warpage) and lower overall cost.
The Fi-PoP package system is meant to deliver increased functional integration in a smaller form factor, flexibility in stacking conventional memory packages on top, improved final assembly yields, and a lower overall cost compared with conventional PoP solutions. The bottom and top package footprint can be reduced significantly (up to 25% and 65% respectively), thus taking up less board space and decreasing the overall cost of this PoP solution.
One of the problems with the Fi-PoP package system is due to bond wires being required between the top package and the bottom package of the Fi-PoP package system. A mold encapsulant is required to cover and protect the bond wires that leaves only an encapsulant cavity in the center of the top package in which external top packages can be mounted. Thus, the encapsulant cavity limits the size of the packages that can be stacked to the top of the Fi-PoP package.
Another problem is that the encapsulant used for covering the bond wires results in a tall Fi-PoP package.
In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations to produce smaller, more reliable integrated circuit package, it is critical that answers be found for these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.